The present invention relates generally to field emitter arrays, and more particularly to a process for fabricating self-aligned micron-sized field emitter arrays.
Recently there has been considerable interest in field emitter arrays for reasons discussed by H. F. Gray et al. in "A Vacuum Field Effect Transistor Using Silicon Field Emitter Arrays", IEDM, 1986, pages 776-779. Field emitter arrays typically comprise a metal/insulator/metal film sandwich with a cellular array of holes through the upper metal and insulator layers, leaving the edges of the upper metal layer (which serves as an accelerator electrode) effectively exposed to the upper surface of the lower metal layer (which serves as an emitter electrode). A number of conically-shaped electron emitter elements are mounted on the lower metal layer and extend upwardly therefrom such that their respective tips are located in respective holes in the upper metal layer. If appropriate voltages are applied between the emitter electrode, accelerator electrode, and an anode located above the accelerator electrode, electrons are caused to flow from the respective cone tips to the anode. Further details regarding these devices may be found in the papers by C. A. Spindt, "A Thin-Film Field-Emission Cathode", Journal of Applied Physics, Vol. 39, No. 7, June 1986, pages 3504-3505, C. A. Spindt et al., "Physical Properties of Thin-Film Field Emission Cathodes with Molybdenum Cones", Journal of Applied Physics, Vol. 47, No. 12, December 1976, pages 5248-5263, and C. A. Spindt et al., "Recent Progress in Low-Voltage Field-Emission Cathode Development", Journal de Physique, Vol. 45, No. C-9, December 1984, pages 269-278, and in U.S. Pat. No. 3,453,478 to K. R. Shoulders et al. and U.S. Pat. Nos. 3,665,241 and 3,755,704 to C. A. Spindt et al. Additional patents disclosing methods for fabricating field emitter array devices are U.S. Pat. No. 3,921,022 to J. D. Levine, U.S. Pat. No. 3,998,678 to S. Fukase et al., U.S. Pat. No. 4,008,412 to I. Yuito et al., U.S. Pat. No. 4,307,507 to H. F. Gray et al., and U.S. Pat. No. 4,513,308 to R. F. Greene et al.
In the conventional approaches to fabrication of field emitter arrays, precise alignment and hole size control has been very difficult to achieve, because of the very small geometries and tolerances in the devices. Typically, in order to obtain precise alignment, it has been necessary to employ a difficult and time-consuming mask step to insure proper alignment and formation.
Accordingly, it would be advantageous to have a process of fabricating field emitter arrays that was self-aligning and that is less difficult and costly to implement.